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1

Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests

Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal

Journal:

Journal of Electronic Testing

Year:

1997

Language:

english

File:

PDF, 152 KB

english, 1997

2

[IEEE 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) - Amherst, MA, USA (2015.10.12-2015.10.14)] 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) - Quest for a quantum search algorithm for testing stuck-at faults in digital circuits

Venkatasubramanian, Muralidharan, Agrawal, Vishwani D., Janaher, James J.

Year:

2015

Language:

english

File:

PDF, 31.06 MB

english, 2015

3

[IEEE 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (Formerly known as SOI Conference) - Monterey, CA, USA (2013.10.7-2013.10.10)] 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) - Dual-threshold design of sub-threshold circuits

Yao, Jia, Agrawal, Vishwani D.

Year:

2013

Language:

english

File:

PDF, 208 KB

english, 2013

4

[IEEE 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) - Delhi, NCR, India (2019.1.5-2019.1.9)] 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) - Two-Pattern ∆IDDQ Test for Recycled IC Detection

Chowdhury, Prattay, Guin, Ujjwal, Singh, Adit D., Agrawal, Vishwani D.

Year:

2019

Language:

english

File:

PDF, 191 KB

english, 2019

5

[IEEE 2009 IEEE International Symposium on Circuits and Systems - ISCAS 2009 - Taipei, Taiwan (2009.05.24-2009.05.27)] 2009 IEEE International Symposium on Circuits and Systems - Designing variation-tolerance in mixed-signal components of a system-on-chip

Jiang, Wei, Agrawal, Vishwani D.

Year:

2009

Language:

english

File:

PDF, 978 KB

english, 2009

6

The Comparative and Concurrent Simulation of discrete-event experiments

Ernst Ulrich, Karen P. Lentz, Jack Arabian, Michael Gustin, Vishwani D. Agrawal, Pier Luca Montessoro

Journal:

Journal of Electronic Testing

Year:

1992

Language:

english

File:

PDF, 1.13 MB

english, 1992

7

[IEEE 2011 IEEE 43rd Southeastern Symposium on System Theory (SSST 2011) - Auburn, AL, USA (2011.03.14-2011.03.16)] 2011 IEEE 43rd Southeastern Symposium on System Theory - A DSP-based ramp test for on-chip high-resolution ADC

Jiang, Wei, Agrawal, Vishwani D.

Year:

2011

Language:

english

File:

PDF, 343 KB

english, 2011

8

[IEEE 2014 IEEE 23rd North Atlantic Test Workshop (NATW) - Johnson City, NY, USA (2014.5.14-2014.5.16)] 2014 IEEE 23rd North Atlantic Test Workshop - Optimal Selection of ATE Frequencies for Test Time Reduction Using Aperiodic Clock

Gunasekar, Sindhu, Agrawal, Vishwani D.

Year:

2014

Language:

english

File:

PDF, 557 KB

english, 2014

9

[IEEE 2020 IEEE 38th VLSI Test Symposium (VTS) - San Diego, CA, USA (2020.4.5-2020.4.8)] 2020 IEEE 38th VLSI Test Symposium (VTS) - Special Session: Survey of Test Point Insertion for Logic Built-in Self-test

Sun, Yang, Millican, Spencer K., Agrawal, Vishwani D.

Year:

2020

File:

PDF, 376 KB

2020

10

Built-in Self-Test for Digital Integrated Circuits

Agrawal, Vishwani D., Lin, Chih-Jen, Rutkowski, Paul W., Wu, Shianling, Zorian, Yervant

Journal:

AT&T Technical Journal

Year:

1994

Language:

english

File:

PDF, 4.64 MB

english, 1994

11

Methods for Synthesizing Testable Sequential Circuits

Cheng, Kwang-Ting, Agrawal, Vishwani D.

Journal:

AT&T Technical Journal

Year:

1991

Language:

english

File:

PDF, 6.19 MB

english, 1991

12

Data-Driven DPPM Estimation and Adaptive Fault Coverage Calibration Using MATLAB®

Kanad Chakraborty, Vishwani D. Agrawal

Journal:

Journal of Electronic Testing

Year:

2012

Language:

english

File:

PDF, 739 KB

english, 2012

13

[IEEE 2013 IEEE International Test Conference (ITC) - Anaheim, CA, USA (2013.09.6-2013.09.13)] 2013 IEEE International Test Conference (ITC) - ATE test time reduction using asynchronous clock period

Venkataramani, Praveen, Agrawal, Vishwani D.

Year:

2013

Language:

english

File:

PDF, 746 KB

english, 2013

14

[IEEE 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012 - Seoul, Korea (South) (2012.05.20-2012.05.23)] 2012 IEEE International Symposium on Circuits and Systems - Impact of process variations on computers used for image processing

Sindia, Suraj, Dai, Fa Foster, Agrawal, Vishwani D., Singh, Virendra

Year:

2012

Language:

english

File:

PDF, 1.01 MB

english, 2012

15

[IEEE 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) - Delhi, NCR, India (2019.1.5-2019.1.9)] 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) - Energy Efficient Power Distribution on Many-Core SoC

Shihab, Mustafa M., Agrawal, Vishwani

Year:

2019

Language:

english

File:

PDF, 1.10 MB

english, 2019

16

Editorial

Vishwani D. Agrawal

Journal:

Journal of Electronic Testing

Year:

2011

Language:

english

File:

PDF, 149 KB

english, 2011

17

[IEEE 21st International Conference on VLSI Design (VLSID 2008) - Hyderabad, India (2008.01.4-2008.01.8)] 21st International Conference on VLSI Design (VLSID 2008) - Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation

Lu, Yuanlin, Agrawal, Vishwani D.

Year:

2008

Language:

english

File:

PDF, 767 KB

english, 2008

18

CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff

Lu, Yuanlin, Agrawal, Vishwani D.

Journal:

Journal of Low Power Electronics

Year:

2006

Language:

english

File:

PDF, 193 KB

english, 2006

19

Graphical $I_{\rm DDQ}$ Signatures Reduce Defect Level and Yield Loss

Rao, Lan, Bushnell, Michael L., Agrawal, Vishwani D.

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2007

Language:

english

File:

PDF, 675 KB

english, 2007

20

[IEEE 25th IEEE VLSI Test Symmposium - Berkeley, CA, USA (2007.05.6-2007.05.10)] 25th IEEE VLSI Test Symmposium (VTS'07) - Delay Test Quality Evaluation Using Bounded Gate Delays

Bose, Soumitra, Agrawal, Vishwani D.

Year:

2007

Language:

english

File:

PDF, 200 KB

english, 2007

21

[IEEE 2012 Southeastern Symposium on System Theory (SSST) - Jacksonville, FL, USA (2012.03.11-2012.03.13)] Proceedings of the 2012 44th Southeastern Symposium on System Theory (SSST) - An efficient algorithm for dual-voltage design without need for level conversion

Allani, Mridula, Agrawal, Vishwani

Year:

2012

Language:

english

File:

PDF, 436 KB

english, 2012

22

[ACM Press Conference proceedings - Orlando, Florida, United States (1990.06.24-1990.06.27)] Conference proceedings on 27th ACM/IEEE design automation conference - DAC '90 - An entropy measure for the complexity of multi-output Boolean functions

Cheng, Kwang-Ting, Agrawal, Vishwani D.

Year:

1990

Language:

english

File:

PDF, 420 KB

english, 1990

23

[ACM Press the 30th international - Dallas, Texas, United States (1993.06.14-1993.06.18)] Proceedings of the 30th international on Design automation conference - DAC '93 - Design for testability for path delay faults in sequential circuits

Chakraborty, Tapan J., Agrawal, Vishwani D., Bushnell, Michael L.

Year:

1993

Language:

english

File:

PDF, 507 KB

english, 1993

24

Editorial

Agrawal, Vishwani D.

Journal:

Journal of Electronic Testing

Year:

2015

Language:

english

File:

PDF, 428 KB

english, 2015

25

Editorial

Agrawal, Vishwani D.

Journal:

Journal of Electronic Testing

Year:

2018

Language:

english

File:

PDF, 271 KB

english, 2018

26

Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures

Roy, Soham, Stiene, Brandon, Millican, Spencer K., Agrawal, Vishwani D.

Journal:

Journal of Electronic Testing

Year:

2020

Language:

english

File:

PDF, 1.03 MB

english, 2020

27

Finite state machine synthesis with fault tolerant test function

Srimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal

Journal:

Journal of Electronic Testing

Year:

1993

Language:

english

File:

PDF, 1.23 MB

english, 1993

28

Editorial

Vishwani D. Agrawal

Journal:

Journal of Electronic Testing

Year:

2010

Language:

english

File:

PDF, 46 KB

english, 2010

29

Editorial

Vishwani D. Agrawal

Journal:

Journal of Electronic Testing

Year:

1998

Language:

english

File:

PDF, 14 KB

english, 1998

30

Editorial

Vishwani D. Agrawal

Journal:

Journal of Electronic Testing

Year:

1999

Language:

english

File:

PDF, 136 KB

english, 1999

31

Editorial

Vishwani D. Agrawal

Journal:

Journal of Electronic Testing

Year:

2002

Language:

english

File:

PDF, 22 KB

english, 2002

32

Editorial

Vishwani D. Agrawal

Journal:

Journal of Electronic Testing

Year:

2002

Language:

english

File:

PDF, 105 KB

english, 2002

33

Editorial

Vishwani D. Agrawal

Journal:

Journal of Electronic Testing

Year:

2012

Language:

english

File:

PDF, 60 KB

english, 2012

34

Editorial

Vishwani D. Agrawal

Journal:

Journal of Electronic Testing

Year:

2013

Language:

english

File:

PDF, 58 KB

english, 2013

35

[IEEE 2014 IEEE 23rd North Atlantic Test Workshop (NATW) - Johnson City, NY, USA (2014.5.14-2014.5.16)] 2014 IEEE 23rd North Atlantic Test Workshop - A New Test Vector Search Algorithm for a Single Stuck-at Fault Using Probabilistic Correlation

Venkatasubramanian, Muralidharan, Agrawal, Vishwani D.

Year:

2014

Language:

english

File:

PDF, 247 KB

english, 2014

36

[IEEE 2012 IEEE 30th VLSI Test Symposium (VTS) - Maui, HI, USA (2012.04.23-2012.04.25)] 2012 IEEE 30th VLSI Test Symposium (VTS) - Net diagnosis using stuck-at and transition fault models

Lixing Zhao,, Agrawal, Vishwani D.

Year:

2012

Language:

english

File:

PDF, 335 KB

english, 2012

37

[IEEE 2012 25th International Conference on VLSI Design - Hyderabad, India (2012.01.7-2012.01.11)] 2012 25th International Conference on VLSI Design - Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock

Shanmugasundaram, Priyadharshini, Agrawal, Vishwani D.

Year:

2012

Language:

english

File:

PDF, 207 KB

english, 2012

38

Editorial

Vishwani D. Agrawal

Journal:

Journal of Electronic Testing

Year:

2004

Language:

english

File:

PDF, 23 KB

english, 2004

39

Editorial

Agrawal, Vishwani D.

Journal:

Journal of Electronic Testing

Year:

2014

Language:

english

File:

PDF, 70 KB

english, 2014

40

[IEEE 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) - Bangalore, India (2007.01.6-2007.01.10)] 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) - Spectral RTL Test Generation for Microprocessors

Yogi, Nitin, Agrawal, Vishwani

Year:

2007

Language:

english

File:

PDF, 197 KB

english, 2007

41

[IEEE 2011 12th Latin American Test Workshop - LATW - Beach of Porto de Galinhas, Brazil (2011.03.27-2011.03.30)] 2011 12th Latin American Test Workshop (LATW) - Testing linear and non-linear analog circuits using moment generating functions

Sindia, Suraj, Agrawal, Vishwani D., Singh, Virendra

Year:

2011

Language:

english

File:

PDF, 264 KB

english, 2011

42

Editorial

Agrawal, Vishwani D.

Journal:

Journal of Electronic Testing

Year:

2016

Language:

english

File:

PDF, 176 KB

english, 2016

43

Editorial

Vishwani D. Agrawal

Journal:

Journal of Electronic Testing

Year:

2016

Language:

english

File:

PDF, 194 KB

english, 2016

44

[IEEE 2018 IEEE 36th VLSI Test Symposium (VTS) - San Francisco, CA, USA (2018.4.22-2018.4.25)] 2018 IEEE 36th VLSI Test Symposium (VTS) - Modeling and test generation for combinational hardware Trojans

Zhou, Ziqi, Guin, Ujjwal, Agrawal, Vishwani D.

Year:

2018

Language:

english

File:

PDF, 217 KB

english, 2018

45

An exact algorithm for selecting partial scan flip-flops

Srimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal

Journal:

Journal of Electronic Testing

Year:

1995

Language:

english

File:

PDF, 955 KB

english, 1995

46

Editorial

Vishwani D. Agrawal

Journal:

Journal of Electronic Testing

Year:

2007

Language:

english

File:

PDF, 53 KB

english, 2007

47

Editorial

Vishwani D. Agrawal

Journal:

Journal of Electronic Testing

Year:

2008

Language:

english

File:

PDF, 47 KB

english, 2008

48

Editorial

Vishwani D. Agrawal

Journal:

Journal of Electronic Testing

Year:

2004

Language:

english

File:

PDF, 20 KB

english, 2004

49

A Test Time Theorem and its Applications

Venkataramani, Praveen, Sindia, Suraj, Agrawal, Vishwani D.

Journal:

Journal of Electronic Testing

Year:

2014

Language:

english

File:

PDF, 521 KB

english, 2014

50

[IEEE 2011 IEEE 29th International Conference on Computer Design (ICCD 2011) - Amherst, MA, USA (2011.10.9-2011.10.12)] 2011 IEEE 29th International Conference on Computer Design (ICCD) - Reduced complexity test generation algorithms for transition fault diagnosis

Zhang, Yu, Agrawal, Vishwani D.

Year:

2011

Language:

english

File:

PDF, 592 KB

english, 2011

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